1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically, generation of an activation timing for a sense amplifier.
2. Description of the Related Art
In general semiconductor memory devices, read-out of data is realized as a sense amplifier detects and amplifies a signal level appearing across bit lines in accordance with the data stored in a memory cell, and outputs it externally.
Accordingly, it is effective to shorten a time between selection of a memory cell and activation of the sense amplifier in order to make the operating period of the semiconductor device faster.
If the sense amplifier is made activated fast, however, data prior to appearing of a sufficient signal level across the bit lines is detected and amplified. This becomes a cause of misreading in this case.
As such, there is a technology which utilizes a replica circuit to generate an appropriate activation timing for the sense amplifier (see, for example, JPH09-259589A). The replica circuit has the same structure as that of a memory cell array, simulates a timing of reading out data from a memory cell, and makes the sense circuit activated at that timing.
However, a timing generated by the replica circuit is normally supplied to the sense circuit via several circuits. Accordingly, because of the influence of the delay times caused by such circuits, it is not true that the replica circuit really and sufficiently simulates the memory cell array.
Moreover, although the replica circuit can replicate a change in the characteristics of a memory cell due to temperature change or the like, there is a problem such that the foregoing circuit cannot reflect such a change.